View SST36VF3204-70-4I-EKE_4074078.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

?2009 silicon storage technology, inc. s71270-04-000 11/09 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. csf is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. data sheet 32 mbit (x8/x16) concurrent superflash sst36vf3203 / sst36vf3204 features: ? organized as 2m x16 or 4m x8 ? dual bank architecture for concurrent read/write operation ? 32 mbit bottom sector protection (in the smaller bank) - sst36vf3203: 8 mbit + 24 mbit ? 32 mbit top sector protection (in the smaller bank) - sst36vf3204: 24 mbit + 8 mbit ? single 2.7-3.6v for read and write operations ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption: ? active current: 6 ma typical ? standby current: 4 a typical ? auto low power mode: 4 a typical ? hardware sector protection/wp# input pin ? protects 8 kword in the smaller bank by driving wp# low and unprotects by driving wp# high ? hardware reset pin (rst#) ? resets the internal state machine to reading array data ? byte# pin ? selects 8-bit or 16-bit mode ? sector-erase capability ? uniform 2 kword sectors ? chip-erase capability ? block-erase capability ? uniform 32 kword blocks ? erase-suspend / erase-resume capabilities ? security id feature ? sst: 128 bits ? user: 256 bytes ? fast read access time ? 70 ns ? latched address and data ? fast erase and program (typical): ? sector-erase time: 18 ms ? block-erase time: 18 ms ? chip-erase time: 35 ms ? program time: 7 s ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bit ? data# polling ? ready/busy# pin ? cmos i/o compatibility ? conforms to common flash memory interface (cfi) ? jedec standards ? flash eeprom pinouts and command sets ? packages available ? 48-ball tfbga (6mm x 8mm) ? 48-lead tsop (12mm x 20mm) ? all non-pb (lead-free) devices are rohs compliant product description the sst36vf320x are 2m x16 or 4m x8 cmos concur- rent read/write flash memory manufactured with sst?s proprietary, high performance cmos superflash technol- ogy. the split-gate cell design and thick-oxide tunneling injector attain better reliab ility and manufacturability com- pared with alternate approaches. the devices write (pro- gram or erase) with a 2.7-3.6v power supply and conform to jedec standard pinouts for x8/x16 memories. featuring high performance word-program, these devices provide a typical program time of 7 sec and use the tog- gle bit, data# polling, or ry/by# to detect the completion of the program or erase operation. to protect against inad- vertent write, the devices have on-chip hardware and soft- ware data protection schemes. designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. data retention is rated at greater than 100 years. these devices are suited for applications that require con- venient and economical updating of program, configura- tion, or data memory. for all system applications, the devices significantly improve performance and reliability, while lowering power consumption. since for any given voltage range, the superflash technology uses less cur- rent to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash technologies. these devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. sst36vf3201c / 1602c32mb (x8/x16) concurrent superflash
2 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 superflash technology provides fixed erase and program times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/program cycles. to meet high-density, surface-mount requirements, these devices are offered in 48-ball tfbga and 48-lead tsop packages. see figures 2 and 3 for pin assignments. device operation memory operation functions are initiated using standard microprocessor write sequences. a command is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, which- ever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. auto low power mode these devices also have the auto lower power mode which puts them in a near standby mode within 500 ns after data has been accessed with a valid read operation. this reduces the i dd active read current to 4 a typically. while ce# is low, the devices exit auto low power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. concurrent read/write operation the dual bank architecture of these devices allows the concurrent read/write operation whereby the user can read from one bank while programming or erasing in the other bank. for example, reading system code in one bank while updating data in the other bank. note: for the purposes of this table, write means to perform block- or sector-erase or program operations as applicable to the appropriate bank. read operation the read operation is controlled by ce# and oe#; both have to be low for the system to obtain data from the out- puts. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is con- sumed. oe# is the output control and is used to gate data from the output pins. the data bus is in a high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram for further details (figure 4). program operation these devices are programmed on a word-by-word or byte-by-byte basis depending on the state of the byte# pin. before programming, one must ensure that the sector which is being programmed is fully erased. the program operation is accomplished in three steps: 1. software data protection is initiated using the three-byte load sequence. 2. address and data are loaded. during the program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. 3. the internal program oper ation is initiated after the rising edge of the fourth we# or ce#, which- ever occurs first. the program operation, once ini- tiated, will be completed typically within 7 s. see figures 5 and 6 for we# and ce# controlled program operation timing diagrams and figure 20 for flowcharts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands issued during an internal program operation are ignored. concurrent read/write state bank 1 bank 2 read no operation read write write read write no operation no operation read no operation write
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 3 ?2009 silicon storage technology, inc. s71270-04-000 11/09 sector- (block-) erase operation these devices offer both sector-erase and block-erase operations. these operations allow the system to erase the devices on a sector-by-sector (or block-by-block) basis. the sector architecture is based on a uniform sector size of 2 kword. the block-erase mode is based on a uniform block size of 32 kword. the sector-erase operation is initiated by executing a six-byte command sequence with a sector- erase command (50h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by execut- ing a six-byte command sequence with block-erase com- mand (30h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the inter- nal erase operation begins after the sixth we# pulse. any commands issued during the sector- or block-erase opera- tion are ignored except erase-suspend and erase- resume. see figures 10 and 11 for timing waveforms. chip-erase operation the devices provide a chip-erase operation, which allows the user to erase all sectors/blocks to the ?1? state. this is useful when a device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. any com- mands issued during the chip-erase operation are ignored. see table 7 for the command sequence, figure 9 for timing diagram, and figure 23 for the flowchart. when wp# is low, any attempt to chip-erase will be ignored. erase-suspend/erase-r esume operations the erase-suspend operation temporarily suspends a sector- or block-erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an erase operation. the operation is executed by issuing a one-byte command sequence with erase-suspend command (b0h). the device automatically enters read mode no more than 10 s after the erase-suspend command had been issued. (t es maximum latency equals 10 s.) valid data can be read from any sector or block that is not suspended from an erase operation. reading at address location within erase- suspended sectors/bl ocks will output dq 2 toggling and dq 6 at ?1?. while in erase-suspend mode, a program operation is allowed except for the sector or block selected for erase-suspend. the software id entry command can also be executed. to resume sector-erase or block-erase operation which has been suspended, the system must issue an erase-resume command. the operation is exe- cuted by issuing a one-byte command sequence with erase resume command (30h) at any address in the last byte sequence. write operation status detection these devices provide one hardware and two software means to detect the completion of a write (program or erase) cycle in order to optimize the system write cycle time. the hardware detection uses the ready/busy# (ry/ by#) output pin. the software detection includes two sta- tus bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a ready/busy# (ry/ by#), a data# polling (dq 7 ), or toggle bit (dq 6 ) read may be simultaneous with the completion of the write cycle. if this occurs, the system may get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious rejection if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the write cycle has completed, other- wise the rejection is valid.
4 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 ready/busy# (ry/by#) the devices include a ready/b usy# (ry/by#) output sig- nal. ry/by# is an open drain output pin that indicates whether an erase or program operation is in progress. since ry/by# is an open drain output, it allows several devices to be tied in parallel to v dd via an external pull-up resistor. after the rising edge of the final we# pulse in the command sequence, the ry/by# status is valid. when ry/by# is actively pulled low, it indicates that an erase or program operation is in progress. when ry/by# is high (ready), the devices may be read or left in standby mode. byte/word (byte#) the device includes a byte# pin to control whether the device data i/o pins operate x8 or x16. if the byte# pin is at logic ?1? (v ih ) the device is in x16 data configuration: all data i/0 pins dq 0 -dq 15 are active and controlled by ce# and oe#. if the byte# pin is at logic ?0?, the device is in x8 data con- figuration: only data i/o pins dq 0 -dq 7 are active and con- trolled by ce# and oe#. the remaining data pins dq 8 - dq 14 are at hi-z, while pin dq 15 is used as the address input a -1 for the least significant bit of the address bus. data# polling (dq 7 ) when the devices are in an internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block-, or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 7 for data# polling (dq 7 ) timing diagram and figure 21 for a flowchart. toggle bits (dq 6 and dq 2 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next opera- tion. the toggle bit is valid after the rising edge of the fourth we# (or ce#) pulse for program operations. for sector-, block-, or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# (or ce#) pulse. dq 6 will be set to ?1? if a read operation is attempted on an erase-sus- pended sector/block. if program operation is initiated in a sector/block not selected in erase-suspend mode, dq 6 will toggle. an additional toggle bit is available on dq 2 , which can be used in conjunction with dq 6 to check whether a particular sector is being actively erased or erase-suspended. table 1 shows detailed status bit information. the toggle bit (dq 2 ) is valid after the rising edge of the last we# (or ce#) pulse of a write operation. see figure 8 for toggle bit timing dia- gram and figure 21 for a flowchart. note: dq 7, dq 6, and dq 2 require a valid address when reading status information. the address must be in the bank where the operation is in progress in order to read the operation sta- tus. if the address is pointing to a different bank (not busy), the device will output array data. data protection the devices provide both hardware and software features to protect nonvolatile data from inadvertent writes. table 1: write operation status status dq 7 dq 6 dq 2 ry/by# normal operation standard program dq7# toggle no toggle 0 standard erase 0 toggle toggle 0 erase- suspend mode read from erase suspended sector/block 1 1 toggle 1 read from non-erase suspended sector/block data data data 1 program dq7# toggle n/a 0 t1.1 1270
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 5 ?2009 silicon storage technology, inc. s71270-04-000 11/09 hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit t he write operation. th is prevents inadvert- ent writes during power-up or power-down. hardware block protection the devices provide hardware block protection which pro- tects the outermost 8 kword in the smaller bank. the block is protected when wp# is held low. when wp# is held low and a block-erase command is issued to the protected black, the data in the outermost 8 kword/16 kbyte section will be protected. the rest of the block will be erased. see tables 3 and 4 for block-protection location. a user can disable block prot ection by driving wp# high. this allows data to be erased or programmed into the pro- tected sectors. wp# must be held high prior to issuing the write command and remain stable until after the entire write operation has completed. if wp# is left floating, it is internally held high via a pull-up resistor, and the boot block is unprotected, enabling program and erase opera- tions on that block. hardware reset (rst#) the rst# pin provides a hardware method of resetting the devices to read array data. when the rst# pin is held low for at least t rp, any in-progress operat ion will terminate and return to read mode (see figure 17) and all output pins are set to high-z. when no internal program/erase opera- tion is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place (see figure 16). the erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. software data protection (sdp) these devices provide the jedec standard software data protection scheme for all data alteration operations, i.e., program and erase. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, provid- ing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of the six-byte sequence. the devices are shipped with the software data protection permanently enabled. see table 7 for the spe- cific software command codes. during sdp command sequence, invalid commands will abort the device to read mode within t rc. the contents of dq 15 -dq 8 can be v il or v ih, but no other value during any sdp command sequence. common flash memory interface (cfi) these devices also contain the cfi information to describe the characteristics of the devices. in order to enter the cfi query mode, the system must write the three-byte sequence, same as the software id entry com- mand with 98h (cfi query command) to address bk x 555h in the last byte sequence. in order to enter the cfi query mode, the system can also use the one-byte sequence with bk x 55h on address and 98h on data bus. see figure 13 for cfi entry and read timing diagram. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 8 through 10. the system must write the cfi exit command to return to read mode from the cfi query mode.
6 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 security id the sst36vf320x devices offer a 136-word security id space. the secure id spac e is divided into two seg- ments?one 128-bit factory programmed segment and one 128-word (256-byte) user-programmed segment. the first segment is programmed and locked at sst with a unique, 128-bit number. the user segment is left un-programmed for the customer to program as desired. to program the user segment of the security id, the user must use the security id program command. end-of-write status is checked by reading the toggle bits. data# polling is not used for security id end-of-write detection. once pro- gramming is complete, the sec id should be locked using the user sec id program lock-out. this disables any future corruption of this space. note that regardless of whether or not the sec id is locked, neither sec id seg- ment can be erased. the secure id space can be queried by executing a three-byte command sequence with query sec id command (88h) at address 555h in the last byte sequence. see figure 15 for timing diagram. to exit this mode, the exit sec id command should be executed. refer to table 7 for more details. product identification the product identification mode identifies the devices and manufacturer. for details, see table 2 for software opera- tion, figure 12 for the software id entry and read timing diagram and figure 22 for the software id entry command sequence flowchart. the addresses a 20 and a 18 indicate a bank address. when the addressed bank is switched to product identification mode, it is possible to read another address from the same bank without issuing a new soft- ware id entry command. the software id entry command may be written to an address within a bank that is in read mode or in erase-suspend mode. the software id entry command may not be written while the device is program- ming or erasing in the other bank. note: bk x = bank address (a 20 -a 18 ) product identification mode exit/cfi mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inadvertent transient condition that appar- ently causes the device to behave abnormally, e.g., not read correctly. please note that the software id exit/cfi exit command is ignored during an internal program or erase operation. see table 7 for the software command code, fig- ure 14 for timing waveform and figure 22 for a flowchart. figure 1: functional block diagram table 2: product identification address data manufacturer?s id bk x 0000h 00bfh device id sst36vf3203 bk x 0001h 7354h sst36vf3204 bk x 0001h 7353h t2.1 1270 1270 b01.0 superflash memory bank 1 i/o buffers superflash memory bank 2 memory address dq 15 /a -1 - dq 0 ce# wp# we# oe# control logic rst# byte# ry/by# address buffers (8 kword / 16 kbyte sector protection)
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 7 ?2009 silicon storage technology, inc. s71270-04-000 11/09 table 3: sst36vf3203, 2m x16 csf bottom dual-bank memory organization (1 of 2) sst36vf3203 block block size address range x8 address range x16 bank 1 ba0 8 kw / 16 kb 000000h?003fffh 000000h?001fffh 24 kw / 48 kb 004000h?00ffffh 002000h?007fffh ba1 32 kw / 64 kb 010000h?01ffffh 008000h?00ffffh ba2 32 kw / 64 kb 020000h?02ffffh 010000h?017fffh ba3 32 kw / 64 kb 030000h?03ffffh 018000h?01ffffh ba4 32 kw / 64 kb 040000h?04ffffh 020000h?027fffh ba5 32 kw / 64 kb 050000h?05ffffh 028000h?02ffffh ba6 32 kw / 64 kb 060000 h?06ffffh 030000h?037fffh ba7 32 kw / 64 kb 070000h?07ffffh 038000h?03ffffh ba8 32 kw / 64 kb 080000 h?08ffffh 040000h?047fffh ba9 32 kw / 64 kb 090000h?09ffffh 048000h?04ffffh ba10 32 kw / 64 kb 0a0000 h?0affffh 050000h?057fffh ba11 32 kw / 64 kb 0b0000h?0bffffh 058000h?05ffffh ba12 32 kw / 64 kb 0c0000h?0cffffh 060000h?067fffh ba13 32 kw / 64 kb 0d0000h?0dffffh 068000h?06ffffh ba14 32 kw / 64 kb 0e0000 h?0effffh 070000h?077fffh ba15 32 kw / 64 kb 0f0000h?0fffffh 078000h?07ffffh bank 2 ba16 32 kw / 64 kb 100000h?10ffffh 080000h?087fffh ba17 32 kw / 64 kb 110000h?11ffffh 088000h?08ffffh ba18 32 kw / 64 kb 120000h?12ffffh 090000h?097fffh ba19 32 kw / 64 kb 130000h?13ffffh 098000h?09ffffh ba20 32 kw / 64 kb 140000h?14ffffh 0a0000h?0a7fffh ba21 32 kw / 64 kb 150000h?15ffffh 0a8000h?0affffh ba22 32 kw / 64 kb 160000h?16ffffh 0b0000h?0b7fffh ba23 32 kw / 64 kb 170000h?17ffffh 0b8000h?0bffffh ba24 32 kw / 64 kb 180000h?18ffffh 0c0000h?0c7fffh ba25 32 kw / 64 kb 190000h?19ffffh 0c8000h?0cffffh ba26 32 kw / 64 kb 1a0000h?1affffh 0d0000h?0d7fffh ba27 32 kw / 64 kb 1b0000h?1bffffh 0d8000h?0dffffh ba28 32 kw / 64 kb 1c0000h?1cffffh 0e0000h?0e7fffh ba29 32 kw / 64 kb 1d0000h?1dffffh 0e8000h?0effffh ba30 32 kw / 64 kb 1e0000h?1effffh 0f0000h?0f7fffh ba31 32 kw / 64 kb 1f0000h?1fffffh 0f8000h?0fffffh ba32 32 kw / 64 kb 200000h?20ffffh 100000h?107fffh ba33 32 kw / 64 kb 210000 h?21ffffh 108 000h?10ffffh ba34 32 kw / 64 kb 220000h?22ffffh 110000h?117fffh ba35 32 kw / 64 kb 230000 h?23ffffh 118 000h?11ffffh ba36 32 kw / 64 kb 240000h?24ffffh 120000h?127fffh ba37 32 kw / 64 kb 250000 h?25ffffh 128 000h?12ffffh ba38 32 kw / 64 kb 260000h?26ffffh 130000h?137fffh ba39 32 kw / 64 kb 270000 h?27ffffh 138 000h?13ffffh ba40 32 kw / 64 kb 280000h?28ffffh 140000h?147fffh ba41 32 kw / 64 kb 290000 h?29ffffh 148 000h?14ffffh
8 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 bank 2 ba42 32 kw / 64 kb 2a0000h?2affffh 150000h?157fffh ba43 32 kw / 64 kb 2b0000h?2bffffh 158000h?15ffffh ba44 32 kw / 64 kb 2c0000h?2cffffh 160000h?167fffh ba45 32 kw / 64 kb 2d0000h?2dffffh 168000h?16ffffh ba46 32 kw / 64 kb 2e0000h?2effffh 170000h?177fffh ba47 32 kw / 64 kb 2f0000h?2fffffh 178000h?17ffffh ba48 32 kw / 64 kb 300000h?30ffffh 180000h?187fffh ba49 32 kw / 64 kb 310000h?31ffffh 188000h?18ffffh ba50 32 kw / 64 kb 320000h?32ffffh 190000h?197fffh ba51 32 kw / 64 kb 330000h?33ffffh 198000h?19ffffh ba52 32 kw / 64 kb 340000h?34ffffh 1a0000h?1a7fffh ba53 32 kw / 64 kb 350000h?35ffffh 1a8000h?1affffh ba54 32 kw / 64 kb 360000h?36ffffh 1b0000h?1b7fffh ba55 32 kw / 64 kb 370000h?37ffffh 1b8000h?1bffffh ba56 32 kw / 64 kb 380000h?38ffffh 1c0000h?1c7fffh ba57 32 kw / 64 kb 390000h?39ffffh 1c8000h?1cffffh ba58 32 kw / 64 kb 3a0000h?3affffh 1d0000h?1d7fffh ba59 32 kw / 64 kb 3b0000h?3bffffh 1d8000h?1dffffh ba60 32 kw / 64 kb 3c0000h?3cffffh 1e0000h?1e7fffh ba61 32 kw / 64 kb 3d0000h?3dffffh 1e8000h?1effffh ba62 32 kw / 64 kb 3e0000h?3effffh 1f0000h?1f7fffh ba63 32 kw / 64 kb 3f0000h ?3fffffh 1f8000h?1fffffh t3.0 1270 table 3: sst36vf3203, 2m x16 csf bottom dual-bank memory organization (continued) (2 of 2) sst36vf3203 block block size address range x8 address range x16
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 9 ?2009 silicon storage technology, inc. s71270-04-000 11/09 table 4: sst36vf3204, 2m x16 csf top dual-bank memory organization (1 of 2) sst36vf3204 block block size address range x8 address range x16 bank 2 ba0 32 kw / 64 kb 000000h?00ffffh 000000h?007fffh ba1 32 kw / 64 kb 010000h?01ffffh 008000h?00ffffh ba2 32 kw / 64 kb 020000h?02ffffh 010000h?017fffh ba3 32 kw / 64 kb 030000h?03ffffh 018000h?01ffffh ba4 32 kw / 64 kb 040000h?04ffffh 020000h?027fffh ba5 32 kw / 64 kb 050000h?05ffffh 028000h?02ffffh ba6 32 kw / 64 kb 060000h?06ffffh 030000h?037fffh ba7 32 kw / 64 kb 070000h?07ffffh 038000h?03ffffh ba8 32 kw / 64 kb 080000h?08ffffh 040000h?047fffh ba9 32 kw / 64 kb 090000h?09ffffh 048000h?04ffffh ba10 32 kw / 64 kb 0a0000h?0affffh 050000h?057fffh ba11 32 kw / 64 kb 0b0000h?0bffffh 058000h?05ffffh ba12 32 kw / 64 kb 0c0000h?0cffffh 060000h?067fffh ba13 32 kw / 64 kb 0d0000h?0dffffh 068000h?06ffffh ba14 32 kw / 64 kb 0e0000h?0effffh 070000h?077fffh ba15 32 kw / 64 kb 0f0000h?0fffffh 078000h?07ffffh ba16 32 kw / 64 kb 100000h?10ffffh 080000h?087fffh ba17 32 kw / 64 kb 110000h?11ffffh 088000h?08ffffh ba18 32 kw / 64 kb 120000h?12ffffh 090000h?097fffh ba19 32 kw / 64 kb 130000h?13ffffh 098000h?09ffffh ba20 32 kw / 64 kb 140000h?14ffffh 0a0000h?0a7fffh ba21 32 kw / 64 kb 150000h?15ffffh 0a8000h?0affffh ba22 32 kw / 64 kb 160000h?16ffffh 0b0000h?0b7fffh ba23 32 kw / 64 kb 170000h?17ffffh 0b8000h?0bffffh ba24 32 kw / 64 kb 180000h?18ffffh 0c0000h?0c7fffh ba25 32 kw / 64 kb 190000h?19ffffh 0c8000h?0cffffh ba26 32 kw / 64 kb 1a0000h?1affffh 0d0000h?0d7fffh ba27 32 kw / 64 kb 1b0000h?1bffffh 0d8000h?0dffffh ba28 32 kw / 64 kb 1c0000h?1cffffh 0e0000h?0e7fffh ba29 32 kw / 64 kb 1d0000h?1dffffh 0e8000h?0effffh ba30 32 kw / 64 kb 1e0000h?1effffh 0f0000h?0f7fffh ba31 32 kw / 64 kb 1f0000h?1fffffh 0f8000h?0fffffh ba32 32 kw / 64 kb 200000h?20ffffh 100000h?107fffh ba33 32 kw / 64 kb 210000h?21ffffh 108000h?10ffffh ba34 32 kw / 64 kb 220000h?22ffffh 110000h?117fffh ba35 32 kw / 64 kb 230000h?23ffffh 118000h?11ffffh ba36 32 kw / 64 kb 240000h?24ffffh 120000h?127fffh ba37 32 kw / 64 kb 250000h?25ffffh 128000h?12ffffh ba38 32 kw / 64 kb 260000h?26ffffh 130000h?137fffh ba39 32 kw / 64 kb 270000h?27ffffh 138000h?13ffffh ba40 32 kw / 64 kb 280000h?28ffffh 140000h?147fffh ba41 32 kw / 64 kb 290000h?29ffffh 148000h?14ffffh ba42 32 kw / 64 kb 2a0000h?2affffh 150000h?157fffh
10 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 bank 2 ba43 32 kw / 64 kb 2b0000h?2bffffh 158000h?15ffffh ba44 32 kw / 64 kb 2c0000h?2cffffh 160000h?167fffh ba45 32 kw / 64 kb 2d0000h?2dffffh 168000h?16ffffh ba46 32 kw / 64 kb 2e0000h?2effffh 170000h?177fffh ba47 32 kw / 64 kb 2f0000h?2fffffh 178000h?17ffffh bank 1 ba48 32 kw / 64 kb 300000h?30ffffh 180000h?187fffh ba49 32 kw / 64 kb 310000h?31ffffh 188000h?18ffffh ba50 32 kw / 64 kb 320000h?32ffffh 190000h?197fffh ba51 32 kw / 64 kb 330000h?33ffffh 198000h?19ffffh ba52 32 kw / 64 kb 340000h?34ffffh 1a0000h?1a7fffh ba53 32 kw / 64 kb 350000h?35ffffh 1a8000h?1affffh ba54 32 kw / 64 kb 360000h?36ffffh 1b0000h?1b7fffh ba55 32 kw / 64 kb 370000h?37ffffh 1b8000h?1bffffh ba56 32 kw / 64 kb 380000h?38ffffh 1c0000h?1c7fffh ba57 32 kw / 64 kb 390000h?39ffffh 1c8000h?1cffffh ba58 32 kw / 64 kb 3a0000h?3affffh 1d0000h?1d7fffh ba59 32 kw / 64 kb 3b0000h?3bffffh 1d8000h?1dffffh ba60 32 kw / 64 kb 3c0000h?3cffffh 1e0000h?1e7fffh ba61 32 kw / 64 kb 3d0000h?3dffffh 1e8000h?1effffh ba62 32 kw / 64 kb 3e0000h?3effffh 1f0000h?1f7fffh ba63 24 kw / 48 kb 3f0000h?3fbfffh 1f8000h?1fdfffh 8 kw / 16 kb 3fc000h?3fffffh 1fe000h?1fffffh t4.0 1270 table 4: sst36vf3204, 2m x16 csf top dual-bank memory organization (continued) (2 of 2) sst36vf3204 block block size address range x8 address range x16
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 11 ?2009 silicon storage technology, inc. s71270-04-000 11/09 figure 2: pin assignments for 48-ball tfbga (6mm x 8mm) figure 3: pin assignments for 48-lead tsop (12mm x 20mm) a13 a9 we# ry/by# a7 a3 a12 a8 rst# wp# a17 a4 a14 a10 nc a18 a6 a2 a15 a11 a19 a20 a5 a1 a16 dq7 dq5 dq2 dq0 a0 byte# dq14 dq12 dq10 dq8 ce# note* dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss 1270 48-tfbga p1.0 top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h note* = dq 15 /a -1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1270 48-tsop p02.0 standard pinout top view die up a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# rst# nc wp# ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte# v ss dq15/a -1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0
12 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 table 5: pin description symbol name functions a 20 -a 0 address inputs to provide memory addresses. during sector-erase and hardware sector protection, a 20 -a 11 address lines will select the sector. during block-erase a 20 -a 15 address lines will select the block. dq 14 -dq 0 data input/output to output data during read cycles and receive input data during write cycles data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. dq 15 /a -1 data input/output and lbs address dq 15 is used as data i/o pin when in x16 mode (byte# = ?1?) a -1 is used as the lsb address pin when in x8 mode (byte# = ?0?) ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers we# write enable to control the write operations rst# hardware reset to reset and return the device to read mode ry/by# ready/busy# to output the status of a program or erase operation ry/by# is a open drain output, so a 10k - 100k pull-up resistor is required to allow ry/by# to transition high indicating the device is ready to read. wp# write protect to protect and unprotect top or bo ttom 8 kword (4 outermost sectors) from erase or program operation. byte# word/byte configuration to select 8-bit or 16-bit mode. v dd power supply to provide 2.7-3.6v power supply voltage v ss ground nc no connection unconnected pins t5.0 1270 table 6: operation modes selection mode ce# oe# we# rst# dq 7 -dq 0 dq 15 -dq 8 address byte# = v ih byte# = v il read v il v il v ih v ih d out d out dq 14 -dq 8 = high z a in program v il v ih v il v ih d in d in dq 15 = a -1 a in erase v il v ih v il v ih x 1 1. x can be v il or v ih , but no other value. x high z sector or block address, 555h for chip-erase standby v ihc xx v ihc high z high z high z x write inhibit x v il xv ih high z / d out high z / d out high z x xxv ih v ih high z / d out high z / d out high z x product identification software mode v il v il v ih v ih manufacturer?s id (bfh) manufacturer?s id (00h) high z see table 7 device id 2 2. device id = sst36vf3203 = 7354h, sst36vf3204 = 7353h device id 2 high z reset x x x v il high z high z high z x t6.1 1270
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 13 ?2009 silicon storage technology, inc. s71270-04-000 11/09 table 7: software command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 555h aah 2aah 55h 555h a0h wa 3 data sector-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa x 4 50h block-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba x 4 30h chip-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h erase-suspend xxxh b0h erase-resume xxxh 30h query sec id 5 555h aah 2aah 55h 555h 88h user security id word-program 555h aah 2aah 55h 555h a5h siwa 6 data user security id program lock-out 7 555h aah 2aah 55h 555h 85h xxxh 0000h software id entry 8,9 555h aah 2aah 55h bk x 4 555h 90h cfi query entry 9 555h aah 2aah 55h bk x 4 555h 98h cfi query entry 9 bk x 4 55h 98h software id exit/ cfi exit/ sec id exit 10,11 555h aah 2aah 55h 555h f0h software id exit/ cfi exit/ sec id exit 10,11 xxh f0h t7.1 1270 1. address format a 10 -a 0 (hex), addresses a 20 -a 11 can be v il or v ih , but no other value (unless otherwise stated), for the command sequence when in x16 mode. when in x8 mode, addresses a 20 -a 12, address a -1, and dq 14 -dq 8 can be v il or v ih , but no other value (unless otherwise stated), for the command sequence. 2. dq 15 -dq 8 can be v il or v ih , but no other value, for the command sequence 3. wa = program word address 4. sa x for sector-erase; uses a 20 -a 11 address lines ba x for block-erase; uses a 20 -a 15 address lines bk x for bank address; uses a 20 -a 18 address lines 5. for sst36vf3203 the security id address range is: (x16 mode) = 100000h to 100087h,(x8 mode) = 100000h to 10010fh sst id is read at address range(x16 mode) = 100000h to 100007h (x8 mode) = 100000h to 10000fh user id is read at address range(x16 mode) = 100008h to 100087h (x8 mode) = 100010h to 10010fh lock status is read at address 1000ffh (x16) or 1001ffh (x8). unlocked: dq3 = 1 / locked: dq3 = 0. for sst36vf3204 the security id address range is:(x16 mode) = 000000h to 000087h, (x8 mode) = 000000h to 00010fh sst id is read at address range (x16 m ode) = 000000h to 000007h (x8 mode) = 000000h to 00000fh user id is read at address range (x16 m ode) = 000008h to 000087h (x8 mode) = 000010h to 00010fh lock status is read at address 0000ffh (x16) or 0001ffh (x8). unlocked: dq3 = 1 / locked: dq3 = 0 6. siwa = valid word addresses for user sec id for sst36vf3203 user id valid address range is (x16 mode) = 100008h-100087h (x8 mode) = 100010h-10010fh. for sst36vf3204 user id valid address range is (x16 mode) = 000008h-000087h (x8 mode) = 000010h-00010fh. all 4 cycles of user security id program and program lock- out must be completed before going back to read-array mode. 7. the user security id program lock-out command must be executed in x16 mode (byte#=v ih ). 8. the device does not remain in software product identification mode if powered down. 9. a 20, a 19, and a 18 = bk x (bank address): address of the bank that is switched to software id/cfi mode with a 17 -a 1 = 0;sst manufacturer?s id = 00bfh, is read with a 0 = 0 sst36vf3203 device id = 7354h, is read with a 0 = 1 sst36vf3204 device id = 7353h, is read with a 0 = 1 10. both software id exit operations are equivalent 11. if users never lock after programming, user sec id can be pr ogrammed over the previously unpr ogrammed bits (data=1) using th e user sec id mode again (the programmed ?0? bits cannot be reversed to ?1?).
14 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 table 8: cfi query identification string 1 address x16 mode address x8 mode data 2 description 10h 20h 0051h query unique ascii string ?qry? 11h 22h 0052h 12h 24h 0059h 13h 26h 0002h primary oem command set 14h 28h 0000h 15h 2ah 0000h address for primary extended table 16h 2ch 0000h 17h 2eh 0000h alternate oem command set (00h = none exists) 18h 30h 0000h 19h 32h 0000h address for alternate oem extended table (00h = none exits) 1ah 34h 0000h t8.1 1270 1. refer to cfi publication 100 for more details. 2. in x8 mode, only the lower byte of data is output. table 9: system interface information address x16 mode address x8 mode data 1 1. in x8 mode, only the lower byte of data is output. description 1bh 36h 0027h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 38h 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 3ah 0000h v pp min (00h = no v pp pin) 1eh 3ch 0000h v pp max (00h = no v pp pin) 1fh 3eh 0004h typical time out for program 2 n s (2 4 = 16 s) 20h 40h 0000h typical time out for min size buffer program 2 n s (00h = not supported) 21h 42h 0004h typical time out for individual sector/block-erase 2 n ms (2 4 = 16 ms) 22h 44h 0006h typical time out for chip-erase 2 n ms (2 6 = 64 ms) 23h 46h 0001h maximum time out for program 2 n times typical (2 1 x 2 4 = 32 s) 24h 48h 0000h maximum time out for buffer program 2 n times typical 25h 4ah 0001h maximum time out for individual sector-/block-erase 2 n times typical (2 1 x 2 4 = 32 ms) 26h 4ch 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 6 = 128 ms) t9.0 1270
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 15 ?2009 silicon storage technology, inc. s71270-04-000 11/09 table 10: device geometry information address x16 mode address x8 mode data 1 description 27h 4eh 0016h device size = 2 n bytes (16h = 22; 2 22 = 4 mbyte) 28h 50h 0002h flash device interface description; 0002h = x8/x16 asynchronous interface 29h 52h 0000h 2ah 54h 0000h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 56h 0000h 2ch 58h 0002h number of erase sector /block sizes supported by device 2dh 5ah 003fh block information (y + 1 = number of blocks; z x 256b = block size) 2eh 5ch 0000h y = 63 + 1 = 64 blocks (003fh = 63) 2fh 5eh 0000h 30h 60h 0001h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) 31h 62h 00ffh sector information (y + 1 = numb er of sectors; z x 256b = sector size) 32h 64h 0003h y = 1023 + 1 = 1024 sectors (03ffh = 1023) 33h 66h 0010h 34h 68h 0000h z = 16 x 256 bytes = 4 kbyte/sector (0010h = 16) t10.2 1270 1. in x8 mode, only the lower byte of data is output.
16 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma operating range range ambient temp v dd extended -20c to +85c 2.7-3.6v industrial -40c to +85c 2.7-3.6v ac conditions of test input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 18 and 19
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 17 ?2009 silicon storage technology, inc. s71270-04-000 11/09 table 11: dc operating characteristics v dd = 2.7-3.6v symbol parameter limits test conditions freq min max units i dd 1 active v dd current read 5 mhz 15 ma ce#=v il, we#=oe#=v ih 1 mhz 4 ma program and erase 30 ma ce#=we#=v il , oe#=v ih concurrent read/write 5 mhz 45 ma ce#=v il, oe#=v ih 1 mhz 35 ma i sb standby v dd current 20 a ce#, rst#=v dd 0.3v i alp auto low power v dd current 20 a ce#=0.1v, v dd =v dd max we#=v dd -0.1v address inputs=0.1v or v dd -0.1v i rt reset v dd current 20 a rst#=gnd i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i liw input leakage current on wp# pin and rst# pin 10 a wp#=gnd to v dd , v dd =v dd max rst#=gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7 v dd v dd +0.3 v v dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v dd +0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t11.1 1270 1. address input = v ilt /v iht, v dd =v dd max (see figure 18) table 12: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t12.0 1270 table 13: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 10 pf c in 1 input capacitance v in = 0v 10 pf t13.0 1270 table 14: reliability characteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t14.0 1270
18 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 ac characteristics table 15: read cycle timing parameters v dd = 2.7-3.6v symbol parameter min max units t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 35 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 16 ns t ohz 1 oe# high to high-z output 16 ns t oh 1 output hold from address change 0 ns t rp 1 rst# pulse width 500 ns t rhr 1 rst# high before read 50 ns t ry 1,2 2. this parameter applies to sector-erase, block-erase, and program operations. this parameter does not apply to chip-erase operations. rst# pin low to read mode 20 s t15.1 1270 table 16: program/erase cycle timing parameters symbol parameter min max units t bp program time 10 s t as address setup time 0 ns t ah address hold time 40 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 50 ms t es erase-suspend latency 10 s t by 1,2 2. this parameter applies to sector-erase, block-erase, and program operations. this parameter does not apply to chip-erase operations. ry/by# delay time 90 ns t br 1 bus recovery time 0 s t16.1 1270
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 19 ?2009 silicon storage technology, inc. s71270-04-000 11/09 figure 4: read cycle timing diagram figure 5: we# controlled program cycle timing diagram 1270 f03.0 addresses dq 15-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 1270 f04.0 addresses dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs ce# 555 2aa 555 addr xxaa xx55 xxa0 data word (addr/data) oe# we# ry/by# t by t br note: x can be v il or v ih , but no other value. valid
20 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 figure 6: ce# controlled prog ram cycle timing diagram figure 7: data# polling timing diagram 1270 f05.0 addresses dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# 555 2aa 555 addr xxaa xx55 xxa0 data word (addr/data) oe# ce# t bp ry/by# t by t br note: x can be v il or v ih , but no other value. valid 1270 f06.0 address dq 7 data data # data # data we# oe# ce# t oeh t oe t ce t oes ry/by# t by
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 21 ?2009 silicon storage technology, inc. s71270-04-000 11/09 figure 8: toggle bit timing diagram figure 9: we# controlled chip-erase timing diagram 1270 f07.0 addresses dq 6 we# oe# ce# t oe t oeh t ce two read cycles with same outputs valid data t br 1270 f08.0 addresses dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx10 xx55 xxaa xx80 xxaa 555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled chip-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 16) x can be v il or v ih , but no other value. ry/by# t by valid t br
22 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 figure 10: we# controlled block-erase timing diagram figure 11: we# controlled sector-erase timing diagram 1270 f09.0 addresses dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx30 xx55 xxaa xx80 xxaa ba x oe# ce# six-byte code for block-erase t be t wp note: this device also supports ce# controlled block-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 16) ba x = block address x can be v il or v ih , but no other value. ry/by# valid t by t br 1270 f10.0 addresses dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx50 xx55 xxaa xx80 xxaa sa x oe# ce# six-byte code for sector-erase t se t wp note: this device also supports ce# controlled sector-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 16) sa x = sector address x can be v il or v ih , but no other value. ry/by# t by t br valid
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 23 ?2009 silicon storage technology, inc. s71270-04-000 11/09 figure 12: software id entry and read figure 13: cfi entry and read 1270 f11.1 addresses t ida dq 15-0 we# device id = 7354h for sst36vf3203 and 7353h for sst36vf3204 note: x can be v il or v ih , but no other value. 555 2aa 555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 1270 f12.0 addresses t ida dq 15-0 we# 555 2aa 555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx98 note: x can be v il or v ih , but no other value.
24 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 figure 14: software id exit/cfi exit figure 15: sec id entry 1270 f13.0 addresses dq 15-0 t ida t wp t wph we# 555 2aa 555 three-byte sequence for software id exit and reset oe# ce# xxaa xx55 xxf0 note: x can be v il or v ih , but no other value. 1270 f14.1 address a ms-0 t ida dq 15-0 we# sw0 sw1 sw2 555 2aa 555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx88 note: a ms = most significant address a ms = a 20 for sst39vf3203/3204 wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence x can be v il or v ih , but no other value.
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 25 ?2009 silicon storage technology, inc. s71270-04-000 11/09 figure 16: rst# timing diagram (when no internal operation is in progress) figure 17: rst# timing diagram (during sector- or block-erase operation) 1270 f15.0 ry/by# 0v rst# ce#/oe# t rp t rhr 1270 f16.0 ry/by# ce# oe# t rp t ry t br rst#
26 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 figure 18: ac input/output reference waveforms figure 19: a test load example 1270 f17.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1270 f18.0 to tester to dut c l
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 27 ?2009 silicon storage technology, inc. s71270-04-000 11/09 figure 20: word-program algorithm 1270 f19.0 start load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxa0h address: 555h load address/data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but no other value.
28 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 figure 21: wait options 1270 f20.0 wait t bp , t sce , t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte/word data# polling program/erase completed program/erase completed read byte/word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 29 ?2009 silicon storage technology, inc. s71270-04-000 11/09 figure 22: software product id/cfi/sec id entry command flowcharts 1270 f20.0 load data: xxaah address: 555h software product id entry command sequence load data: xx55h address: 2aah load data: xx90h address: 555h wait t ida read software id load data: xxaah address: 555h cfi query entry command sequence load data: xx55h address: 2aah load data: xx98h address: 555h wait t ida read cfi data load data: xxaah address: 555h software id exit/ cfi exit/sec id command sequence load data: xx55h address: 2aah load data: xxf0h address: 555h wait t ida return to normal operation x can be v il or v ih, but no other value
30 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 figure 23: erase command sequence 1270 f22.0 load data: xxaah address: 555h chip-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx10h address: 555h load data: xxaah address: 555h wait t sce chip erased to ffffh load data: xxaah address: 555h sector-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx50h address: sa x load data: xxaah address: 555h wait t se sector erased to ffffh load data: xxaah address: 555h block-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx30h address: ba x load data: xxaah address: 555h wait t be block erased to ffffh note: x can be v il or v ih, but no other value.
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 31 ?2009 silicon storage technology, inc. s71270-04-000 11/09 product ordering information valid combinations for sst36vf3203 sst36vf3203-70-4e-b3ke sst36vf3203-70-4e-eke sst36vf3203-70-4i-b3ke sst36vf3203-70-4i-eke valid combinations for sst36vf3204 sst36vf3204-70-4e-b3ke sst36vf3204-70-4e-eke sst36vf3204-70-4i-b3ke SST36VF3204-70-4I-EKE note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. environmental attribute e 1 = non-pb package modifier k = 48 balls or leads package type b3 = tfbga (6mm x 8mm) e =tsop (type 1, die up, 12mm x 20mm) temperature range e = extended = -20c to +85c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns bank split 3 = 8 mbit + 24 mbit 4 = 24 mbit + 8 mbit device density 320 = 2 mbit x16 or 4 mbit x8 voltage v = 2.7-3.6v product series 36 = concurrent superflash 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. sst 36 vf 320x - 70 - 4e - b3k e xx x x xxx x - xxx -xx -xx x x
32 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 packaging diagrams 48- ball t hin - profile , f ine - pitch b all g rid a rray (tfbga) 6 mm x 8 mm sst p ackage c ode : b3k a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.35 0.05 1.10 0.10 0.12 6.00 0.20 0.45 0.05 (48x) a1 corner 8.00 0.20 0.80 4.00 0.80 5.60 48-tfbga-b3k-6x8-450mic-4 note: 1. complies with jedec publication 95, mo-210, variant 'ab-1', although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 1mm
data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 33 ?2009 silicon storage technology, inc. s71270-04-000 11/09 48- lead t hin s mall o utline p ackage (tsop) 12 mm x 20 mm sst p ackage c ode : ek 1.05 0.95 0.70 0.50 18.50 18.30 20.20 19.80 0.70 0.50 12.20 11.80 0.27 0.17 0.15 0.05 48-tsop-ek-8 note: 1. complies with jedec publication 95 mo-142 dd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm 0?- 5? detail pin # 1 identifier 0. 50 bsc
34 data sheet 32 mbit concurrent superflash sst36vf3203 / sst36vf3204 ?2009 silicon storage technology, inc. s71270-04-000 11/09 table 17: revision history number description date 00 ? initial release of data sheet feb 2005 01 ? updated ?erase-suspend/erase-resume operations? on page 3 ? updated footnote 5 and added footnote 7 to table 7 on page 13 ? updated cfi query identification in table 8 on page 14 ? updated device geometry information in table 10 on page 15 ? updated t es parameter from 20 s to 10 s in table 16 on page 18 ? in ?product ordering information? on page 31 ? removed all mpns for packages containing pb (b3k/ek) ? removed all commercial temperature mpns ? added extended temperature mpns for all devices sep 2005 02 ? removed industrial grade reference ? changed to data sheet ? removed non-pb reference ? updated bank information ? changes toe from 30ns to 35ns, table 15, page 18 may 2006 03 ? re-added industrial grade reference jul 2006 04 ? edited tby ty/by# delay time in table 15 on page 18 from 90ns min to 90ns max nov 2009 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

▲Up To Search▲

Price & Availability of SST36VF3204-70-4I-EKE

	To Download SST36VF3204-70-4I-EKE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .